1. Field of the Invention
The present invention relates generally to level converting circuits, and more particularly, level converting circuits for coupling different types of logical circuits to each other and a method of converting the voltage level of a logic signal.
2. Description of the Background Art
Various level converting circuits have been developed for coupling an ECL (emitter coupled logic) circuit capable of a high speed operation and a CMOS (complementary metal oxide semiconductor) circuit of a small power consumption. FIG. 5 is a circuit diagram showing one example of a conventional level converting circuit for converting a signal of an ECL level to a signal of an MOS level. The level converting circuit of FIG. 5 is described in Japanese Patent Laying Open No. 60-132416, No. 62-123825 and the like.
In FIG. 5, an ECL buffer circuit 1 comprises a bipolar ECL circuit, which receives an ECL level signal A and outputs complementary ECL level signals a and a. A level converting circuit 2a comprises two current mirror circuits, which receive the complementary signals a and a of the ECL level and supply MOS level complementary signals b and b. A bipolar-CMOS (BiCMOS) driver circuit 3 comprises a composite of a bipolar transistor and a CMOS circuit, and is used for increasing a driving capability of the complementary signals b and b outputted from the level converting circuit 2a.
The ECL buffer circuit 1 is comprised of an ECL input circuit portion including NPN transistors 11 and 12, and a resistance 13, a current switching portion including resistances 14, 15 and 19, and NPN transistors 16, 17 and 18, and an ECL output circuit portion including NPN transistors 20, 21, 22 and 23, and resistances 24 and 25.
The above described structure of the ECL buffer circuit is disclosed in Japanese Patent Laying Open No. 60-217725.
Normally, a relatively high power supply voltage V.sub.CC is set to 0 V, and a relatively low power supply voltage V.sub.EE is set to -4.5 V or -5.2 V. A signal A of the ECL level is applied to a base of the NPN transistor 11. The "H" level of the signal A is -0.9 V, and the "L" level thereof is -1.7 V. The signals a and a of the ECL level are respectively outputted from respective emitters of the NPN transistors 20 and 21 which are emitter follower transistors. The "H" level of the signals a and a attains a level of about -0.8 V which is equal to a level where the power supply voltage V.sub.CC is less by the amount of a base-emitter voltage V.sub.BE of the emitter follower transistors 20, 21. The "L" level V.sub.L of the signals a and a will be obtained by the following equation, EQU V.sub.L =V.sub.CC -I.multidot.R-V.sub.BE ( 1)
wherein I is a value of a current flowing through the resistance 14 or 15, and R is a resistance value of the resistance 14 or 15. A reference voltage V.sub.BB is applied to a base of the NPN transistor 17. An input threshold is set by the reference voltage V.sub.BB. A reference voltage V.sub.CS1 is applied to bases of the NPN transistors 12, 18, 22 and 23. Current values of the current switching portion and the ECL output circuit portion are set by the reference voltage V.sub.CS1.
The level converting circuit 2a is comprised of a first current mirror circuit including P-channel metal oxide semiconductor (PMOS) transistors 46 and 47 and, N-channel metal oxide semiconductor (NMOS) transistors 48 and 49, and a second current mirror including PMOS transistors 50 and 51 and NMOS transistors 52 and 53. The signal a is applied to gates of the PMOS transistors 46 and 51, and the signal a is applied to gates of the PMOS transistors 47 and 50. The signal b of the MOS level is supplied from a connection point between the PMOS transistor 47 and the NMOS transistor 49, and the signal b of the NMOS level is outputted from a connection point between the PMOS transistor 51 and the NMOS transistor 53. The "H" level of the signals b and b is the power supply voltage V.sub.CC, and the "L" level thereof is the power supply voltage V.sub.EE.
The BiCMOS driver circuit 3 is comprised of a first CMOS inverter including a PMOS transistor 32 and an NMOS transistor 33, a second CMOS inverter including a PMOS transistor 38 and an NMOS transistor 39, a first base control circuit including NMOS transistors 34 and 35, a second base control circuit including NMOS transistors 40 and 41, and NPN transistors 36, 37, 42 and 43. The NPN transistors 36 and 37 and the NPN transistors 42 and 43 are series connected between the relatively high power supply voltage V.sub.CC and the relatively low power supply voltage V.sub.EE as shown in FIG. 5.
The first CMOS inverter drives the NPN transistor 36 and the second CMOS inverter drives the NPN transistor 42. The first base control circuit controls a base current of the NPN transistor 37, and the second base control circuit controls a base current of the NPN transistor 43. A signal C of the BiCMOS level is outputted from a connection point between the NPN transistor 36 and the NPN transistor 37, and a signal C of the BiCMOS level is outputted from a connection point between the NPN transistor 42 and the NPN transistor 43. The "H" level of the signals C and is -0.4 V, and the "L" level thereof is -4.1 V or -4.8 V.
Now, description will be given of operation of the circuit of FIG. 5 in which the signal A of the ECL level changes from the "H" level (-0.9 V) to the "L" level (-1.7 V).
When the signal A of the ECL level applied to the base of the NPN transistor 11 changes from the "H" level to the "L" level, a collector potential of the NPN transistor 16 changes from the "L" level to the "H" level, and on the contrary, a collector potential of the NPN transistor 17 changes from the "H" level to the "L" level, whereby an emitter potential of the NPN transistor 21 (signal a) changes from the "L" level to the "H" level, and on the contrary, an emitter potential of the NPN transistor 20 (signal a) changes from the "H" level to the "L" level. As described above, the "H" level of the signal a and a is a level of about -0.8 V which is lowered from the power supply voltage V.sub.CC by the amount of base-emitter voltage V.sub.BE of the emitter follower transistor. The "L" level of the signals a and a can be obtained by the above described equation ( 1). If an amplitude of an output of the current switching portion is represented as 1 V, the "L" level of the signal a and a will be -1.8 V.
Since the signal a changes from the "L-" level to the "H" level and the signal a changes from the "H" level to the "L" level as described above, the PMOS transistors 46 and 51 are turned on and the PMOS transistors 47 and 50 are turned off. In addition, the NMOS transistor 49 is turned on and the NMOS transistor 53 is turned off. Accordingly, the signal b outputted from the level converting circuit 2a changes from the "L" level (power supply voltage V.sub.EE) to the "H" level (power supply voltage V.sub.CC), and the signal b changes from the "H" level (power supply voltage V.sub.CC) to the "L" level (power supply voltage V.sub.EE). These signals b and b are of the MOS level. Accordingly, they are converted from the ECL level to the MOS level.
Since the level converting circuit 2a is comprised of the MOS transistors, its driving capability is limited. Accordingly, the driving capability is increased by BiCMOS driver circuit 3. When the signal b changes from the "L" level (power supply voltage V.sub.EE) to the "H" level (power supply voltage V.sub.CC), the PMOS transistor 38 is turned off, and the NMOS transistors 39 and 40 are turned on, whereby the NMOS transistor 41 is turned off. Accordingly, the NPN transistor 42 is turned off and the NPN transistor 43 is turned off. As a result, the signal C outputted from the BiCMOS driver circuit 3 attains the "L" level (V.sub.EE +0.4 V).
On the other hand, as described above, when the signal b changes from the "H" level (power supply voltage V.sub.CC) to the "L" level (power supply voltage V.sub.EE), PMOS transistor 32 is turned on, and NMOS transistors 33 and 34 are turned off, so that NMOS transistor 35 is turned off. Accordingly, NPN transistor 36 is turned on, and NPN transistor 37 is turned off. As a result, the signal C supplied by BiCMOS driver circuit 3 attains the "H" level (V.sub.CC -0.4 V).
When ECL signal A changes from the "L" level to the "H" level, signal a attains an ECL "L" level and signal a attains "H" level by the same operation. Therefore, the signal b attains the "L" level of the MOS level, and the signal b attains the "H" level of the MOS level. In addition, the signal C attains the "L" level of the BiCMOS level, and the signal C attains the "H" level of the BiCMOS level.
As the foregoing, a logical level is converted between the ECL circuit and the MOS circuit.
However, in the above described conventional level converting circuit, two pairs of MOS current mirror circuits are required in order to obtain complementary signals of the MOS level. Therefore, a layout area is increased. In addition, increase of a size of a transistor constituting a MOS current mirror circuit for increasing the operation speed, results in increase of current consumption. For example, it is confirmed by the present inventor that in the level converting circuit 2a, if a gate width W of the PMOS transistors 46, 47, 50 and 51 is 40 .mu.m, and a gate width W of the NMOS transistors 48, 49, 52 and 53 is 20 .mu.m, a switching time from the inputs to the outputs b, b of the level converting circuit 2a will be about 1.1 ns whereas a current flowing through the level converting circuit 2a will be about 2.5 mA. It is also confirmed by the present inventor that in the level converting circuit 2a, if a gate width W of the PMOS transistors 46, 47, 50 and 51 is smaller, about 10 .mu.m, and a gate width W of the NMOS transistors 48, 49, 52 and 53 is smaller, about 5 .mu.m, a consumption current will be smaller, about 0.8 mA, whereas a switching time from the inputs to the outputs b, b of the level converting circuit 2a will be longer, about 1.5 ns.
Accordingly, if a conventional level converting circuit is used in an address buffer of a semiconductor memory device of 64K bit, the number of addresses is 16, so that a current as large as 40 mA is consumed in the level converting circuit alone. Thus, a conventional level converting circuit also has a serious problem regarding a power consumption.